1. Field of Invention
The present invention relates to a method for forming a charge storage structure. More particularly, the present invention relates to a method for forming DRAM's charge storage structure.
2. Description of Related Art
In most dynamic random access memory (DRAM), data is usually stored in an array of capacitors on a semiconductor wafer. In general, a capacitor that is able to discharge is referred to as in a logic "1" state, while a capacitor that needs to be charged is referred to as in a logic "0" state. Hence, a bit of binary data is stored in each capacitor.
Normally, a capacitor having a high charge storage capacity is greatly desired. In other words, a capacitor with a high capacitance is very much in demand. The capacitance of a capacitor is largely determined by the separation between the top and the bottom electrodes. Since there is a dielectric layer between the top and the bottom electrodes, the distance of separation is determined by the thickness of the dielectric layer. Therefore, when the dielectric layer is made very thin, a higher capacitance is obtained.
Another factor that affects the capacitance of a capacitor is the dielectric constant of the material used to fabricate the dielectric layer. Charge storage capacity can be increased simply by using a material having a high dielectric constant.
Although dielectric thickness and dielectric constant are two main factors affecting the capacitance, some other factors will also affect the capacitance of a capacitor indirectly. One of these factors is related to properties of the selected dielectric material, for example, the charge leakage rate through the dielectric material and the breakdown voltage of the dielectric material. In mass production of capacitors, charge leakage and voltage breakdown not only will be related to the dielectric material used, but also will be affected by the quality of dielectric thin film produced. For example, if the thin dielectric film contains pinhole structure leading to a charge leakage, then the quality of the dielectric material in a DRAM capacitor is consider poor. Similarly, if the dielectric material has a low breakdown voltage, then the dielectric material can only be used for devices in low voltage operation.
In recent years, attempts have been made to increase the dielectric constant of dielectric material used in a DRAM capacitor, for example, such material includes tantalum oxide (Ta.sub.2 O.sub.5). Tantalum oxide has a dielectric constant of about 25, whereas silicon dioxide (SiO.sub.2) has a dielectric constant of only about 3.9. However, the conventional method of forming a tantalum oxide thin film often leads to non-uniformity of quality and unstable dielectric constant. In addition, during the deposition of tantalum oxide, a native oxide may be grown in between the polysilicon electrode and the tantalum oxide layer that frequently leads to non-uniformity in the tantalum oxide layer, and a lowering of the dielectric constant. If annealing operation is performed one or several times in an atmosphere with oxygen, then leakage current from the tantalum oxide layer will be reduced. Furthermore, oxygen vacancy and other abnormalities of a thin film can be reduced as well. However, annealing will help the oxygen atom diffuse through the tantalum oxide, and oxidizing the polysilicon electrode beneath the tantalum oxide layer.
In view of the above problems, when the dielectric material such as tantalum oxide is deposited, native oxide on the polysilicon electrode surface of a wafer must be removed or its original growth limited. One method of removing the native oxide layer from the surface of the polysilicon electrode includes using a wet etching method. However, this method is difficult to remove the native oxide layer completely. Moreover, when there is a transfer of wafer from one reaction chamber to another, probability of reforming the native oxide is high.
In light of the foregoing, there is a need in the art an improved method for forming a charge storage structure.